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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [apps/] [dhry/] [Makefile] - Rev 397

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397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4948d 08h /openrisc/trunk/orpsocv2/sw/apps/dhry/Makefile
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4951d 07h /openrisc/trunk/orpsocv2/sw/apps/dhry/Makefile
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 4996d 14h /openrisc/trunk/orpsocv2/sw/dhry/Makefile
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5000d 04h /openrisc/trunk/orpsocv2/sw/dhry/Makefile
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5283d 05h /openrisc/trunk/orpsocv2/sw/dhry/Makefile
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5361d 01h /openrisc/trunk/orpsocv2/sw/dhry/Makefile
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5412d 12h /openrisc/trunk/orpsocv2/sw/dhry/Makefile
6 Checking in ORPSoCv2 julius 5475d 00h /openrisc/trunk/orpsocv2/sw/dhry/Makefile

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