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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Rev 530

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530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4764d 06h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
489 ORPSoC sw cleanup. Remove warnings. julius 4838d 03h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4838d 03h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4845d 06h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4866d 05h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
470 ORPSoC OR1200 crt0 updates. julius 4870d 05h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4924d 15h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4945d 01h /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 4978d 00h /crt0.S
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 4993d 21h /crt0.S
349 ORPSoCv2 update with new software and makefile update julius 4995d 01h /crt0.S

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