OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] - Rev 412

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4945d 03h /openrisc/trunk/orpsocv2/sw/tests/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4945d 15h /openrisc/trunk/orpsocv2/sw/tests/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4946d 15h /openrisc/trunk/orpsocv2/sw/tests/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4947d 03h /openrisc/trunk/orpsocv2/sw/tests/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4948d 09h /openrisc/trunk/orpsocv2/sw/tests/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4950d 14h /openrisc/trunk/orpsocv2/sw/tests/
395 ORPSoCv2 moving ethernet tests to correct place julius 4953d 13h /openrisc/trunk/orpsocv2/sw/tests/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4953d 14h /openrisc/trunk/orpsocv2/sw/tests/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.