OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-basic.S] - Rev 530

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE		 julius 4764d 16h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4925d 01h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4945d 11h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
349 ORPSoCv2 update with new software and makefile update julius 4995d 11h /or1200-basic.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.