OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 630

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
630 orpsoc: add Digilent Atlys spartan6 board backend

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4850d 13h /
629 orpsoc: add Digilent Atlys spartan6 board or1ksim configuration

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4850d 13h /
628 orpsoc: add Digilent Atlys spartan6 board Makefiles

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4850d 13h /
627 orpsoc: add Digilent Atlys spartan6 board rtl

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4850d 13h /
626 Fix to support GCC 4.6 by disabling -Werror. jeremybennett 4859d 03h /
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4859d 04h /
624 add missing delay slot instruction
vPortDisableInterrupts
vPortEnableInterrupts
filepang 4860d 09h /
623 cleanup source code
Demo/OpenRISC_SIM_GCC/arch/support.h
Demo/OpenRISC_SIM_GCC/arch/interrupts.h
Demo/OpenRISC_SIM_GCC/arch/link.ld

add gpio driver

add gpio base address definition
filepang 4861d 00h /
622 update uart driver for support multiple uart cores
from http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/sw/drivers/uart
filepang 4861d 02h /
621 update sim.cfg for newer version of Or1ksim.
remove unused files.
cleanup source code.

insert non-local jump(setjmp) in xPortStartScheduler. now xPortStartScheduler() will
be returned by xPortEndScheduler().
filepang 4862d 18h /
620 remove unused file
cleanup makefile
update uart_init(), disable interrupt before initialize.
jeremybennett 4863d 07h /
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4871d 19h /
618 Remove unused parameter Tp olof 4872d 02h /
617 Set tx_negedge correctly (Fixes bug #12) olof 4876d 05h /
616 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4877d 03h /
615 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4877d 03h /
614 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4877d 03h /
613 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4877d 03h /
612 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4877d 03h /
611 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4877d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.