OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] - Rev 491

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
491 ORPSoC or1200_monitor update. julius 5034d 10h /
490 Updates to fix spurious test failures and register scheduling. jeremybennett 5038d 16h /
489 ORPSoC sw cleanup. Remove warnings. julius 5043d 22h /
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 5043d 23h /
487 ORPSoC main software makefile update julius 5046d 21h /
486 ORPSoC updates, mainly software, i2c driver julius 5046d 21h /
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 5051d 01h /
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 5051d 23h /
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 5054d 01h /
482 Don't hardcode tool versions in help text olof 5055d 14h /
481 OR1200 Update. RTL and spec. julius 5067d 08h /
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 5068d 06h /
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 5069d 05h /
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 5070d 21h /
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 5071d 05h /
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 5071d 22h /
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 5072d 01h /
474 uC/OS-II port linker flags updated. julius 5072d 07h /
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 5073d 01h /
472 Various changes which improve the quality of the tracing. jeremybennett 5073d 02h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.