URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] - Rev 486

Rev	Log message	Author	Age	Path
466	ORPSoC updates: Add new test to determine processor's capabilities. Fix up typo in example in spiflash app README	julius	4878d 18h	/openrisc/
465	ORPSoC SPI flash load Makefile and README updates.	julius	4879d 08h	/openrisc/
464	More ORPmon updates.	julius	4879d 09h	/openrisc/
463	ORPmon update	julius	4879d 12h	/openrisc/
462	ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM models updated.	julius	4879d 17h	/openrisc/
461	Updated to be much stricter about usage.	jeremybennett	4881d 12h	/openrisc/
460	Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes.	jeremybennett	4881d 14h	/openrisc/
459	Add option to bld-all.sh to explicitly set control load of make, and fix typos.	julius	4881d 20h	/openrisc/
458	or1ksim testsuite updates	julius	4882d 18h	/openrisc/
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	4891d 08h	/openrisc/