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Rev Log message Author Age Path
977 Added store buffer. lampret 7945d 01h /
976 Added store buffer lampret 7945d 01h /
975 First checkin lampret 7945d 01h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7945d 03h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7947d 07h /
972 Interrupt suorces fixed. simons 7947d 08h /
971 Now even keyboard test passes. simons 7947d 10h /
970 Testbench is now running on ORP architecture platform. simons 7947d 23h /
969 Checking in except directory. lampret 7948d 15h /
968 Checking in utils directory. lampret 7948d 15h /
967 Checking in mul directory. lampret 7948d 15h /
966 Checking in cbasic directory. lampret 7948d 15h /
965 Checking in basic directory. lampret 7948d 15h /
964 Checking in support directory. lampret 7948d 15h /
963 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7948d 15h /
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7948d 15h /
961 uart16550 RTL files renamed/added/removed. lampret 7948d 15h /
960 Directory cleanup. lampret 7948d 15h /
959 Fixed size of generic flash/sram to exactly 2MB lampret 7949d 15h /
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7949d 15h /

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