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Rev Log message Author Age Path
981 First checkin. lampret 7944d 22h /
980 Removed sim.tcl that shouldn't be here. lampret 7944d 22h /
979 Removed old test case binaries. lampret 7944d 22h /
978 Added variable delay for SRAM. lampret 7944d 22h /
977 Added store buffer. lampret 7944d 22h /
976 Added store buffer lampret 7944d 22h /
975 First checkin lampret 7944d 22h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7945d 00h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7947d 05h /
972 Interrupt suorces fixed. simons 7947d 05h /
971 Now even keyboard test passes. simons 7947d 08h /
970 Testbench is now running on ORP architecture platform. simons 7947d 21h /
969 Checking in except directory. lampret 7948d 12h /
968 Checking in utils directory. lampret 7948d 12h /
967 Checking in mul directory. lampret 7948d 12h /
966 Checking in cbasic directory. lampret 7948d 12h /
965 Checking in basic directory. lampret 7948d 12h /
964 Checking in support directory. lampret 7948d 12h /
963 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7948d 12h /
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7948d 12h /

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