URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [initial/] - Rev 1782

Rev	Log message	Author	Age	Path
1765		root	5533d 06h	/or1k/tags/initial/
811	This commit was manufactured by cvs2svn to create tag 'initial'.		8058d 18h	/tags/initial/
199	Initial import	simons	8271d 21h	/trunk/
198	Moved from testbench.old	simons	8274d 08h	/trunk/
197	This is not used any more.	simons	8274d 08h	/trunk/
196	Configuration SPRs added.	simons	8274d 08h	/trunk/
195	New test added.	simons	8274d 08h	/trunk/
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8274d 16h	/trunk/
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8274d 17h	/trunk/
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8275d 02h	/trunk/
191	Added UART jitter var to sim config	chris	8275d 22h	/trunk/
190	Added jitter initialization	chris	8275d 22h	/trunk/
189	fixed mode handling for tick facility	chris	8275d 22h	/trunk/
188	fixed PIC interrupt controller	chris	8275d 22h	/trunk/
187	minor change to clear pending exception	chris	8275d 22h	/trunk/
186	major change to UART structure	chris	8275d 22h	/trunk/
185	major change to UART code	chris	8275d 22h	/trunk/
184	modified decode for trace debugging	chris	8275d 22h	/trunk/
183	changed special case for PICSR	chris	8275d 22h	/trunk/
182	updated exception handling procedures	chris	8275d 22h	/trunk/