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[/] [or1k/] [tags/] [nog_patch_56/] [or1ksim/] [cache/] - Rev 1765

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Rev Log message Author Age Path
1765 root 5546d 18h /or1k/tags/nog_patch_56/or1ksim/cache/
1437 This commit was manufactured by cvs2svn to create tag 'nog_patch_56'. 6987d 01h /or1k/tags/nog_patch_56/or1ksim/cache/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 6987d 01h /or1k/tags/nog_patch_56/or1ksim/cache/
1406 Fix the declaration of `sec' in reg_ic_sec nogj 6987d 01h /or1k/tags/nog_patch_56/or1ksim/cache/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 6987d 01h /or1k/tags/nog_patch_56/or1ksim/cache/
1402 Do what dc_clock() did in mtspr() and remove it nogj 6987d 01h /or1k/tags/nog_patch_56/or1ksim/cache/
1386 Rework exception handling nogj 6993d 05h /or1k/tags/nog_patch_56/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7002d 05h /or1k/tags/nog_patch_56/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7021d 05h /or1k/tags/nog_patch_56/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7027d 20h /or1k/tags/nog_patch_56/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7037d 00h /or1k/tags/nog_patch_56/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7050d 03h /or1k/tags/nog_patch_56/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7241d 18h /or1k/tags/nog_patch_56/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7406d 18h /or1k/tags/nog_patch_56/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7749d 18h /or1k/tags/nog_patch_56/or1ksim/cache/
1099 cvs bug fixed markom 7836d 06h /or1k/tags/nog_patch_56/or1ksim/cache/
1085 Bug fixed. simons 7848d 20h /or1k/tags/nog_patch_56/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 7938d 09h /or1k/tags/nog_patch_56/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 7940d 00h /or1k/tags/nog_patch_56/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 7945d 20h /or1k/tags/nog_patch_56/or1ksim/cache/

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