OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [insight/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5529d 20h /or1k/tags/rel-0-3-0-rc2/insight/
1753 This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc2'. 5649d 03h /or1k/tags/rel-0-3-0-rc2/insight/
1751 These are the changes to support Or1ksim 0.3.0rc2. Most significantly they provide GDB RSP support. They also fix 5 outstanding bugs and satisfy one new feature request. jeremybennett 5649d 05h /or1k/tags/rel-0-3-0-rc2/insight/
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.
jeremybennett 5679d 01h /or1k/tags/rel-0-3-0-rc2/insight/
1672 Store instructions don't modify any register. Don't mark them as such in the
arch. definitions
nogj 6675d 23h /or1k/tags/rel-0-3-0-rc2/insight/
1656 Pass the instruction operands as part of the op_queue structure. nogj 6675d 23h /or1k/tags/rel-0-3-0-rc2/insight/
1605 Execute l.ff1 instruction nogj 6738d 01h /or1k/tags/rel-0-3-0-rc2/insight/
1597 Fix parsing the destination register nogj 6750d 02h /or1k/tags/rel-0-3-0-rc2/insight/
1590 Added l.fl1 lampret 6753d 00h /or1k/tags/rel-0-3-0-rc2/insight/
1557 Fix most warnings issued by gcc4 nogj 6812d 10h /or1k/tags/rel-0-3-0-rc2/insight/
1554 fixed l.maci encoding phoenix 6829d 21h /or1k/tags/rel-0-3-0-rc2/insight/
1552 Update most config.guess and config.sub scripts. robertmh 6857d 23h /or1k/tags/rel-0-3-0-rc2/insight/
1475 l.rfe does not have a delay slot. Don't mark it as such. nogj 6943d 00h /or1k/tags/rel-0-3-0-rc2/insight/
1452 Implement a dynamic recompiler to speed up the execution nogj 6970d 03h /or1k/tags/rel-0-3-0-rc2/insight/
1444 Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h nogj 6970d 03h /or1k/tags/rel-0-3-0-rc2/insight/
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 6970d 03h /or1k/tags/rel-0-3-0-rc2/insight/
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 6985d 06h /or1k/tags/rel-0-3-0-rc2/insight/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7020d 01h /or1k/tags/rel-0-3-0-rc2/insight/
1346 Remove the global op structure nogj 7033d 05h /or1k/tags/rel-0-3-0-rc2/insight/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7033d 05h /or1k/tags/rel-0-3-0-rc2/insight/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.