OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [testbench/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5550d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1753 This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc2'. 5670d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.		 jeremybennett 5699d 23h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1745 These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. jeremybennett 5735d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1725 Add tests for the sign extenstion instructions. nogj 6696d 19h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6742d 16h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1578 Put consecutive asm statements into one __asm__() block to prevent gcc from scheduleing other instructions between them. nogj 6809d 05h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1568 Update config files nogj 6832d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1566 Make the timer test emit the correct success protocol nogj 6832d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1565 Revert previous `fix' to accept the correct return code nogj 6832d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1552 Update most config.guess and config.sub scripts. robertmh 6878d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1549 Spelling fixes nogj 6894d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1540 * Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer.		 nogj 6894d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1523 Bring config files up-to-date with recent changes nogj 6900d 05h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1498 Correct a couple of tests nogj 6915d 04h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1497 Print more verbose ouput nogj 6915d 04h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 6943d 05h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1446 Cosmetic fixes nogj 6991d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1424 Update the config files for the tests to the new format nogj 6991d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/
1422 Remove the useless include "sys/time.h" nogj 6991d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.