URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_3/] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5546d 06h	/or1k/tags/rel_3
995	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7939d 02h	/tags/rel_3
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7939d 02h	/trunk
993	Fixed IMMU bug.	lampret	7939d 02h	/trunk
992	A bug when cache enabled and bus error comes fixed.	simons	7939d 11h	/trunk
991	Different memory controller.	simons	7939d 12h	/trunk
990	Test is now complete.	simons	7939d 12h	/trunk
989	c++ is making problems so, for now, it is excluded.	simons	7940d 19h	/trunk
988	ORP architecture supported.	simons	7941d 11h	/trunk
987	ORP architecture supported.	simons	7941d 18h	/trunk
986	outputs out of function are not registered anymore	markom	7941d 19h	/trunk
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7942d 07h	/trunk
984	Disable SB until it is tested	lampret	7942d 07h	/trunk
983	First checkin	lampret	7942d 09h	/trunk
982	Moved to sim/bin	lampret	7942d 09h	/trunk
981	First checkin.	lampret	7942d 09h	/trunk
980	Removed sim.tcl that shouldn't be here.	lampret	7942d 09h	/trunk
979	Removed old test case binaries.	lampret	7942d 09h	/trunk
978	Added variable delay for SRAM.	lampret	7942d 09h	/trunk
977	Added store buffer.	lampret	7942d 09h	/trunk