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[/] [or1k/] [tags/] [rel_3/] [or1200/] - Rev 1765

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Rev Log message Author Age Path
1765 root 5535d 10h /or1k/tags/rel_3/or1200/
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7928d 06h /or1k/tags/rel_3/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7928d 06h /or1k/tags/rel_3/or1200/
993 Fixed IMMU bug. lampret 7928d 06h /or1k/tags/rel_3/or1200/
984 Disable SB until it is tested lampret 7931d 11h /or1k/tags/rel_3/or1200/
977 Added store buffer. lampret 7931d 13h /or1k/tags/rel_3/or1200/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7935d 03h /or1k/tags/rel_3/or1200/
960 Directory cleanup. lampret 7935d 03h /or1k/tags/rel_3/or1200/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7936d 02h /or1k/tags/rel_3/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7938d 03h /or1k/tags/rel_3/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7938d 03h /or1k/tags/rel_3/or1200/
942 Delayed external access at page crossing. lampret 7938d 03h /or1k/tags/rel_3/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 7950d 07h /or1k/tags/rel_3/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 7966d 10h /or1k/tags/rel_3/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8002d 16h /or1k/tags/rel_3/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8002d 16h /or1k/tags/rel_3/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8002d 16h /or1k/tags/rel_3/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8073d 16h /or1k/tags/rel_3/or1200/
794 Added again just recently removed full_case directive lampret 8073d 16h /or1k/tags/rel_3/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8073d 16h /or1k/tags/rel_3/or1200/

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