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[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 1765

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1765 root 5547d 11h /or1k/tags/rel_5/or1200/
1056 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7915d 07h /or1k/tags/rel_5/or1200/
1055 Removed obsolete comment. lampret 7915d 07h /or1k/tags/rel_5/or1200/
1054 Fixed a combinational loop. lampret 7915d 07h /or1k/tags/rel_5/or1200/
1053 Disabled cache inhibit atttribute. lampret 7915d 07h /or1k/tags/rel_5/or1200/
1040 Updated the script. lampret 7922d 13h /or1k/tags/rel_5/or1200/
1039 Added linter directory. lampret 7922d 13h /or1k/tags/rel_5/or1200/
1038 Fixed a typo, reported by Taylor Su. lampret 7922d 14h /or1k/tags/rel_5/or1200/
1037 First import of the new synopsys DC scripts. lampret 7922d 15h /or1k/tags/rel_5/or1200/
1036 Removed old synthesis scripts. lampret 7922d 15h /or1k/tags/rel_5/or1200/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7923d 04h /or1k/tags/rel_5/or1200/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7923d 15h /or1k/tags/rel_5/or1200/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7924d 04h /or1k/tags/rel_5/or1200/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7927d 09h /or1k/tags/rel_5/or1200/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7927d 11h /or1k/tags/rel_5/or1200/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7934d 08h /or1k/tags/rel_5/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7940d 08h /or1k/tags/rel_5/or1200/
993 Fixed IMMU bug. lampret 7940d 08h /or1k/tags/rel_5/or1200/
984 Disable SB until it is tested lampret 7943d 12h /or1k/tags/rel_5/or1200/
977 Added store buffer. lampret 7943d 14h /or1k/tags/rel_5/or1200/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7947d 04h /or1k/tags/rel_5/or1200/
960 Directory cleanup. lampret 7947d 04h /or1k/tags/rel_5/or1200/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7948d 04h /or1k/tags/rel_5/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7950d 04h /or1k/tags/rel_5/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7950d 04h /or1k/tags/rel_5/or1200/
942 Delayed external access at page crossing. lampret 7950d 04h /or1k/tags/rel_5/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 7962d 08h /or1k/tags/rel_5/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 7978d 12h /or1k/tags/rel_5/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8014d 18h /or1k/tags/rel_5/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8014d 18h /or1k/tags/rel_5/or1200/

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