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[/] [or1k/] [trunk/] [or1200/] [rtl/] - Rev 1774

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Rev Log message Author Age Path
1765 root 5547d 19h /or1k/trunk/or1200/rtl/
1736 See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts. lampret 6614d 17h /or1k/trunk/or1200/rtl/
1583 First Import jcastillo 6786d 06h /or1k/trunk/or1200/rtl/
1582 Added support for RAMB16 Xilinx4/Spartan3 primitives jcastillo 6786d 06h /or1k/trunk/or1200/rtl/
1339 revert to the old l.sfxxi behavior phoenix 7065d 07h /or1k/trunk/or1200/rtl/
1337 du_hwbkpt disabled when debug unit not implemented andreje 7071d 09h /or1k/trunk/or1200/rtl/
1336 sign/zero extension for l.sfxxi instructions corrected andreje 7071d 09h /or1k/trunk/or1200/rtl/
1335 flag for l.cmov instruction added andreje 7071d 09h /or1k/trunk/or1200/rtl/
1334 l.ff1 and l.cmov instructions added andreje 7071d 09h /or1k/trunk/or1200/rtl/
1293 Non-functional changes. Coding style fixes. lampret 7284d 00h /or1k/trunk/or1200/rtl/
1292 GPR0 hardwired to zero. lampret 7284d 00h /or1k/trunk/or1200/rtl/
1291 Changed behavior of the simulation generic models lampret 7284d 00h /or1k/trunk/or1200/rtl/
1288 By default l.cust5 insns are disabled lampret 7313d 22h /or1k/trunk/or1200/rtl/
1284 Added some l.cust5 custom instructions as example lampret 7313d 22h /or1k/trunk/or1200/rtl/
1273 Add support for 512B instruction cache. simont 7345d 07h /or1k/trunk/or1200/rtl/
1268 Merged branch_qmem into main tree. lampret 7348d 09h /or1k/trunk/or1200/rtl/
1267 Merged branch_qmem into main tree. lampret 7348d 10h /or1k/trunk/or1200/rtl/
1228 Exception prefix configuration changed to match branch_qmem configuration. simons 7429d 09h /or1k/trunk/or1200/rtl/
1211 New wb_biu for iwb interface. lampret 7470d 18h /or1k/trunk/or1200/rtl/
1208 Added useless signal genpc_stop_refetch. lampret 7470d 18h /or1k/trunk/or1200/rtl/

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