OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1ksim/] [pm/] - Rev 1774

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5554d 01h /or1k/trunk/or1ksim/pm/
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.
jeremybennett 5703d 06h /or1k/trunk/or1ksim/pm/
1745 These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. jeremybennett 5739d 05h /or1k/trunk/or1ksim/pm/
1744 Changes to bring behavior into line with the current OpenRISC 1000 specification and support GDB 6.8. A couple of small bugs with handling xterms and opening the remote debug channel are also fixed. Header files have been added to sources in Makefile.am files where they are missing, so that "make tags" will include them. Makefile.in files have been regenerated due to these changes. jeremybennett 5740d 05h /or1k/trunk/or1ksim/pm/
1649 Mark as many functions as possible static nogj 6700d 04h /or1k/trunk/or1ksim/pm/
1576 configure updates phoenix 6813d 01h /or1k/trunk/or1ksim/pm/
1508 Remove m{f,t}spr calls where we can access the spr directly nogj 6903d 12h /or1k/trunk/or1ksim/pm/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 6994d 08h /or1k/trunk/or1ksim/pm/
1376 aclocal && autoconf && automake phoenix 7028d 12h /or1k/trunk/or1ksim/pm/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7035d 03h /or1k/trunk/or1ksim/pm/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7044d 06h /or1k/trunk/or1ksim/pm/
1249 Downgrading back to automake-1.4 lampret 7414d 00h /or1k/trunk/or1ksim/pm/
1117 Ignore generated files for CVS purposes sfurman 7757d 01h /or1k/trunk/or1ksim/pm/
997 PRINTF should be used instead of printf; command redirection repaired markom 7945d 15h /or1k/trunk/or1ksim/pm/
970 Testbench is now running on ORP architecture platform. simons 7953d 02h /or1k/trunk/or1ksim/pm/
876 Beta release of ATA simulation rherveille 7997d 01h /or1k/trunk/or1ksim/pm/
805 kbd, fb, vga devices now uses scheduler markom 8080d 16h /or1k/trunk/or1ksim/pm/
517 some performance optimizations markom 8176d 10h /or1k/trunk/or1ksim/pm/
500 Added .cvsignore files for annoying generated files erez 8178d 13h /or1k/trunk/or1ksim/pm/
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8248d 13h /or1k/trunk/or1ksim/pm/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.