URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1039

Rev	Log message	Author	Age	Path
1039	Added linter directory.	lampret	7922d 01h	/
1038	Fixed a typo, reported by Taylor Su.	lampret	7922d 02h	/
1037	First import of the new synopsys DC scripts.	lampret	7922d 03h	/
1036	Removed old synthesis scripts.	lampret	7922d 03h	/
1035	Added optional l.div/l.divu insns. By default they are disabled.	lampret	7922d 16h	/
1034	Fixed encoding for l.div/l.divu.	lampret	7922d 20h	/
1033	If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].	lampret	7923d 03h	/
1032	Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.	lampret	7923d 16h	/
1031	Setting phy to 10Mbps full duplex.	simons	7924d 07h	/
1030	Ethernet configured for 10Mbps.	simons	7925d 04h	/
1029	Typing error fixed.	simons	7925d 05h	/
1028	Import.	ivang	7925d 05h	/
1027	PRINTF/printf mess fixed.	simons	7925d 13h	/
1026	rtems-20020807 import	ivang	7925d 23h	/
1025	PRINTF/printf mess fixed.	simons	7926d 02h	/
1024	Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes.	simons	7926d 11h	/
1023	Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.	lampret	7926d 21h	/
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	7927d 00h	/
1021	* empty log message *	rherveille	7931d 02h	/
1020	Fixed several bugs Working version, tested on Bender hardware	rherveille	7931d 02h	/