OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1214

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7467d 01h /
1213 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7471d 12h /
1212 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7471d 12h /
1211 New wb_biu for iwb interface. lampret 7471d 12h /
1210 No functional change. lampret 7471d 12h /
1209 Fixed instantiation name. lampret 7471d 12h /
1208 Added useless signal genpc_stop_refetch. lampret 7471d 12h /
1207 Static exception prefix. lampret 7471d 12h /
1206 Static exception prefix. lampret 7471d 13h /
1205 fix for gdb_debug config phoenix 7477d 21h /
1204 added additional field into executed log wich besides EA also prints PA (physical address) phoenix 7495d 09h /
1203 value stored in ITLB and DTLB match registers was wrong. fixed. phoenix 7495d 09h /
1202 at exception print insn number to ease debugging phoenix 7495d 09h /
1201 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7520d 04h /
1200 mbist signals updated according to newest convention markom 7520d 04h /
1199 Daniel Wiklund: Removed multiple entries of debug/Makefile in configure danwi 7524d 05h /
1198 make it compile on RH 8,9 phoenix 7549d 20h /
1197 disabled ram-init of ps2 (old) +
changed MAC type into DOS type, so that Xilinx ISE can work with it
dries 7555d 01h /
1196 removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se) dries 7555d 02h /
1195 made the project file a little bit more universal dries 7555d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.