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Rev Log message Author Age Path
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7930d 20h /
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7930d 20h /
993 Fixed IMMU bug. lampret 7930d 20h /
992 A bug when cache enabled and bus error comes fixed. simons 7931d 05h /
991 Different memory controller. simons 7931d 05h /
990 Test is now complete. simons 7931d 05h /
989 c++ is making problems so, for now, it is excluded. simons 7932d 13h /
988 ORP architecture supported. simons 7933d 04h /
987 ORP architecture supported. simons 7933d 12h /
986 outputs out of function are not registered anymore markom 7933d 12h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7934d 00h /
984 Disable SB until it is tested lampret 7934d 00h /
983 First checkin lampret 7934d 02h /
982 Moved to sim/bin lampret 7934d 02h /
981 First checkin. lampret 7934d 02h /
980 Removed sim.tcl that shouldn't be here. lampret 7934d 02h /
979 Removed old test case binaries. lampret 7934d 02h /
978 Added variable delay for SRAM. lampret 7934d 02h /
977 Added store buffer. lampret 7934d 02h /
976 Added store buffer lampret 7934d 02h /
975 First checkin lampret 7934d 02h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7934d 04h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7936d 09h /
972 Interrupt suorces fixed. simons 7936d 09h /
971 Now even keyboard test passes. simons 7936d 12h /
970 Testbench is now running on ORP architecture platform. simons 7937d 00h /
969 Checking in except directory. lampret 7937d 16h /
968 Checking in utils directory. lampret 7937d 16h /
967 Checking in mul directory. lampret 7937d 16h /
966 Checking in cbasic directory. lampret 7937d 16h /

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