URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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[/] [or1k_old/] [tags/] [initial/] - Rev 1782

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Rev	Log message	Author	Age	Path
1782		root	5438d 08h	/or1k_old/tags/initial/
1765		root	5549d 00h	/or1k_old/tags/initial/
811	This commit was manufactured by cvs2svn to create tag 'initial'.		8074d 12h	/or1k_old/tags/initial/
199	Initial import	simons	8287d 15h	/or1k_old/tags/initial/
198	Moved from testbench.old	simons	8290d 02h	/or1k_old/tags/initial/
197	This is not used any more.	simons	8290d 02h	/or1k_old/tags/initial/
196	Configuration SPRs added.	simons	8290d 03h	/or1k_old/tags/initial/
195	New test added.	simons	8290d 03h	/or1k_old/tags/initial/
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8290d 11h	/or1k_old/tags/initial/
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8290d 11h	/or1k_old/tags/initial/
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8290d 20h	/or1k_old/tags/initial/
191	Added UART jitter var to sim config	chris	8291d 17h	/or1k_old/tags/initial/
190	Added jitter initialization	chris	8291d 17h	/or1k_old/tags/initial/
189	fixed mode handling for tick facility	chris	8291d 17h	/or1k_old/tags/initial/
188	fixed PIC interrupt controller	chris	8291d 17h	/or1k_old/tags/initial/
187	minor change to clear pending exception	chris	8291d 17h	/or1k_old/tags/initial/
186	major change to UART structure	chris	8291d 17h	/or1k_old/tags/initial/
185	major change to UART code	chris	8291d 17h	/or1k_old/tags/initial/
184	modified decode for trace debugging	chris	8291d 17h	/or1k_old/tags/initial/
183	changed special case for PICSR	chris	8291d 17h	/or1k_old/tags/initial/

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[/] [or1k_old/] [tags/] [initial/] - Rev 1782

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