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[/] [or1k_old/] [tags/] [rel_3/] - Rev 1782

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Rev Log message Author Age Path
1782 root 5438d 11h /or1k_old/tags/rel_3/
1765 root 5549d 03h /or1k_old/tags/rel_3/
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7942d 00h /or1k_old/tags/rel_3/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7942d 00h /or1k_old/tags/rel_3/
993 Fixed IMMU bug. lampret 7942d 00h /or1k_old/tags/rel_3/
992 A bug when cache enabled and bus error comes fixed. simons 7942d 09h /or1k_old/tags/rel_3/
991 Different memory controller. simons 7942d 09h /or1k_old/tags/rel_3/
990 Test is now complete. simons 7942d 09h /or1k_old/tags/rel_3/
989 c++ is making problems so, for now, it is excluded. simons 7943d 17h /or1k_old/tags/rel_3/
988 ORP architecture supported. simons 7944d 08h /or1k_old/tags/rel_3/
987 ORP architecture supported. simons 7944d 16h /or1k_old/tags/rel_3/
986 outputs out of function are not registered anymore markom 7944d 16h /or1k_old/tags/rel_3/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7945d 04h /or1k_old/tags/rel_3/
984 Disable SB until it is tested lampret 7945d 04h /or1k_old/tags/rel_3/
983 First checkin lampret 7945d 06h /or1k_old/tags/rel_3/
982 Moved to sim/bin lampret 7945d 06h /or1k_old/tags/rel_3/
981 First checkin. lampret 7945d 06h /or1k_old/tags/rel_3/
980 Removed sim.tcl that shouldn't be here. lampret 7945d 06h /or1k_old/tags/rel_3/
979 Removed old test case binaries. lampret 7945d 06h /or1k_old/tags/rel_3/
978 Added variable delay for SRAM. lampret 7945d 06h /or1k_old/tags/rel_3/

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