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[/] [pairing/] [trunk/] [rtl/] - Rev 32

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Rev Log message Author Age Path
32 changed surname: Xing -> Hsing. homer.xing 4446d 14h /pairing/trunk/rtl/
31 accurate source code copyright comment header homer.xing 4446d 14h /pairing/trunk/rtl/
30 LGPL header homer.xing 4456d 18h /pairing/trunk/rtl/
29 default net type is wire homer.xing 4463d 15h /pairing/trunk/rtl/
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4463d 18h /pairing/trunk/rtl/
27 definition for undefined wire homer.xing 4463d 18h /pairing/trunk/rtl/
24 LGPL claim in each source hdl file homer.xing 4477d 14h /pairing/trunk/rtl/
23 LGPL license text homer.xing 4477d 14h /pairing/trunk/rtl/
22 Change TAB to space homer.xing 4477d 16h /pairing/trunk/rtl/
17 use logic for $f3m_mux6$ homer.xing 4479d 13h /pairing/trunk/rtl/
12 Simplify the interface of the core. homer.xing 4479d 19h /pairing/trunk/rtl/
11 Cheers! as fast as a rocket homer.xing 4480d 15h /pairing/trunk/rtl/
10 Ho ho, better circuit homer.xing 4481d 09h /pairing/trunk/rtl/
9 Add constrains file for ISE homer.xing 4482d 12h /pairing/trunk/rtl/
8 Finished Tate Pairing. Ha ha ha homer.xing 4482d 13h /pairing/trunk/rtl/
7 Finish inversion @ f33m homer.xing 4490d 18h /pairing/trunk/rtl/
6 add testbench for $f33m$. homer.xing 4491d 18h /pairing/trunk/rtl/
5 rename director : verilog/ -> rtl/ homer.xing 4491d 18h /pairing/trunk/rtl/
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4492d 16h /pairing/trunk/verilog/
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4493d 15h /pairing/trunk/verilog/

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