URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing] - Rev 33

Rev	Log message	Author	Age	Path
33	new email & English name of the author	homer.xing	4457d 12h	/pairing
32	changed surname: Xing -> Hsing.	homer.xing	4457d 13h	/pairing
31	accurate source code copyright comment header	homer.xing	4457d 13h	/pairing
30	LGPL header	homer.xing	4467d 17h	/pairing
29	default net type is wire	homer.xing	4474d 14h	/pairing
28	Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha	homer.xing	4474d 16h	/pairing
27	definition for undefined wire	homer.xing	4474d 17h	/pairing
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4480d 13h	/pairing
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4480d 13h	/pairing
24	LGPL claim in each source hdl file	homer.xing	4488d 13h	/pairing
23	LGPL license text	homer.xing	4488d 13h	/pairing
22	Change TAB to space	homer.xing	4488d 15h	/pairing
21	Add detailed input data capture condition in the document	homer.xing	4488d 15h	/pairing
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4489d 17h	/pairing
19	Update synthesis result	homer.xing	4490d 11h	/pairing
18	add synthesis result	homer.xing	4490d 11h	/pairing
17	use logic for $f3m_mux6$	homer.xing	4490d 12h	/pairing
16	Add synthesis configuration files	homer.xing	4490d 16h	/pairing
15	add document. ha ha ha	homer.xing	4490d 17h	/pairing
14	Move constraint file	homer.xing	4490d 17h	/pairing