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Rev	Log message	Author	Age	Path
33	new email & English name of the author	homer.xing	4452d 09h	/
32	changed surname: Xing -> Hsing.	homer.xing	4452d 10h	/
31	accurate source code copyright comment header	homer.xing	4452d 10h	/
30	LGPL header	homer.xing	4462d 14h	/
29	default net type is wire	homer.xing	4469d 10h	/
28	Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha	homer.xing	4469d 13h	/
27	definition for undefined wire	homer.xing	4469d 13h	/
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4475d 09h	/
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4475d 10h	/
24	LGPL claim in each source hdl file	homer.xing	4483d 10h	/
23	LGPL license text	homer.xing	4483d 10h	/
22	Change TAB to space	homer.xing	4483d 11h	/
21	Add detailed input data capture condition in the document	homer.xing	4483d 12h	/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4484d 14h	/
19	Update synthesis result	homer.xing	4485d 07h	/
18	add synthesis result	homer.xing	4485d 07h	/
17	use logic for $f3m_mux6$	homer.xing	4485d 09h	/
16	Add synthesis configuration files	homer.xing	4485d 12h	/
15	add document. ha ha ha	homer.xing	4485d 13h	/
14	Move constraint file	homer.xing	4485d 14h	/
13	Add document and synthesis directories	homer.xing	4485d 14h	/
12	Simplify the interface of the core.	homer.xing	4485d 15h	/
11	Cheers! as fast as a rocket	homer.xing	4486d 10h	/
10	Ho ho, better circuit	homer.xing	4487d 04h	/
9	Add constrains file for ISE	homer.xing	4488d 08h	/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4488d 09h	/
7	Finish inversion @ f33m	homer.xing	4496d 14h	/
6	add testbench for $f33m$.	homer.xing	4497d 13h	/
5	rename director : verilog/ -> rtl/	homer.xing	4497d 13h	/
4	add testbench	homer.xing	4498d 11h	/

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[/] - Rev 33

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