OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_2/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5527d 12h /pci/tags/rel_2/
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7859d 08h /tags/rel_2/
69 Changed BIST signal names etc.. mihad 7859d 08h /trunk/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7862d 17h /trunk/
67 Changed BIST signals for RAMs. tadejm 7862d 22h /trunk/
66 Changed empty status generation in pciw_fifo_control.v mihad 7866d 08h /trunk/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7869d 06h /trunk/
64 The testcase I just added in previous revision repaired mihad 7869d 09h /trunk/
63 Added additional testcase and changed rst name in BIST to trst mihad 7869d 11h /trunk/
62 Added BIST signals for RAMs. mihad 7872d 03h /trunk/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7880d 03h /trunk/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7880d 05h /trunk/
58 Removed all logic from asynchronous reset network mihad 7885d 05h /trunk/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7885d 11h /trunk/
56 Number of state bits define was removed mihad 7886d 02h /trunk/
55 Changed state machine encoding to true one-hot mihad 7886d 02h /trunk/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7919d 04h /trunk/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7919d 07h /trunk/
52 Oops, never before noticed that OC header is missing mihad 7919d 11h /trunk/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7919d 12h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.