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[/] [pci/] [tags/] [rel_2/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5562d 13h /pci/tags/rel_2
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7894d 08h /tags/rel_2
69 Changed BIST signal names etc.. mihad 7894d 08h /trunk
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7897d 17h /trunk
67 Changed BIST signals for RAMs. tadejm 7897d 22h /trunk
66 Changed empty status generation in pciw_fifo_control.v mihad 7901d 09h /trunk
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7904d 07h /trunk
64 The testcase I just added in previous revision repaired mihad 7904d 09h /trunk
63 Added additional testcase and changed rst name in BIST to trst mihad 7904d 11h /trunk
62 Added BIST signals for RAMs. mihad 7907d 04h /trunk
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7915d 04h /trunk
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7915d 05h /trunk
58 Removed all logic from asynchronous reset network mihad 7920d 05h /trunk
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7920d 11h /trunk
56 Number of state bits define was removed mihad 7921d 02h /trunk
55 Changed state machine encoding to true one-hot mihad 7921d 03h /trunk
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7954d 04h /trunk
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7954d 08h /trunk
52 Oops, never before noticed that OC header is missing mihad 7954d 12h /trunk
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7954d 12h /trunk

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