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[/] [pci/] [tags/] [rel_3/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5543d 05h /pci/tags/rel_3/
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7782d 22h /tags/rel_3/
73 Bug fixes, testcases added. mihad 7782d 22h /trunk/
72 *** empty log message *** mihad 7830d 02h /trunk/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7837d 17h /trunk/
69 Changed BIST signal names etc.. mihad 7875d 01h /trunk/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7878d 10h /trunk/
67 Changed BIST signals for RAMs. tadejm 7878d 15h /trunk/
66 Changed empty status generation in pciw_fifo_control.v mihad 7882d 01h /trunk/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7885d 00h /trunk/
64 The testcase I just added in previous revision repaired mihad 7885d 02h /trunk/
63 Added additional testcase and changed rst name in BIST to trst mihad 7885d 04h /trunk/
62 Added BIST signals for RAMs. mihad 7887d 21h /trunk/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7895d 20h /trunk/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7895d 22h /trunk/
58 Removed all logic from asynchronous reset network mihad 7900d 22h /trunk/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7901d 04h /trunk/
56 Number of state bits define was removed mihad 7901d 19h /trunk/
55 Changed state machine encoding to true one-hot mihad 7901d 19h /trunk/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7934d 21h /trunk/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7935d 00h /trunk/
52 Oops, never before noticed that OC header is missing mihad 7935d 05h /trunk/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7935d 05h /trunk/
50 Got rid of undef directives mihad 7937d 21h /trunk/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7937d 21h /trunk/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7937d 21h /trunk/
47 Known issues repaired mihad 7938d 03h /trunk/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7942d 21h /trunk/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7944d 03h /trunk/
44 Added for testing of Configuration Cycles Type 1 mihad 7944d 03h /trunk/

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