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[/] [pci/] [tags/] [rel_5/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5528d 04h /pci/tags/rel_5/
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7758d 14h /tags/rel_5/
81 Updated synchronization in top level fifo modules. mihad 7758d 14h /trunk/
79 Updated. mihad 7761d 19h /trunk/
78 Old files with wrong names removed. mihad 7761d 19h /trunk/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7761d 19h /trunk/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7764d 19h /trunk/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7767d 20h /trunk/
73 Bug fixes, testcases added. mihad 7767d 20h /trunk/
72 *** empty log message *** mihad 7815d 00h /trunk/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7822d 15h /trunk/
69 Changed BIST signal names etc.. mihad 7859d 23h /trunk/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7863d 08h /trunk/
67 Changed BIST signals for RAMs. tadejm 7863d 13h /trunk/
66 Changed empty status generation in pciw_fifo_control.v mihad 7867d 00h /trunk/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7869d 22h /trunk/
64 The testcase I just added in previous revision repaired mihad 7870d 00h /trunk/
63 Added additional testcase and changed rst name in BIST to trst mihad 7870d 02h /trunk/
62 Added BIST signals for RAMs. mihad 7872d 19h /trunk/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7880d 19h /trunk/

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