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[/] [pci/] [tags/] [rel_7/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5528d 06h /pci/tags/rel_7/
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7562d 20h /tags/rel_7/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7562d 20h /trunk/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7563d 01h /trunk/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7565d 00h /trunk/
109 There was missing path to hdl.var file. tadejm 7568d 21h /trunk/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7568d 21h /trunk/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7568d 22h /trunk/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7573d 20h /trunk/
105 Wrong pci_bridge32.v file included in the project! mihad 7579d 03h /trunk/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7579d 06h /trunk/
103 Added test application and modified files to support it. mihad 7626d 03h /trunk/
102 Cleanup! mihad 7626d 03h /trunk/
101 Added simulation files. mihad 7626d 03h /trunk/
100 Cleanup! mihad 7626d 03h /trunk/
99 Cleanup! mihad 7626d 03h /trunk/
98 Cleanup. mihad 7626d 04h /trunk/
97 Doing a little bit of cleanup. mihad 7626d 04h /trunk/
96 Update! mihad 7626d 04h /trunk/
95 Removed this file, because it was too large - long download time. mihad 7626d 04h /trunk/

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