OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5541d 01h /pci/tags/rel_WB_B3/
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7568d 13h /tags/rel_WB_B3/
119 Added support for WB B3. Some testcases were updated. tadejm 7568d 13h /trunk/
118 Some minor changes due to changes in core. tadejm 7568d 13h /trunk/
117 WB Master is now WISHBONE B3 compatible. tadejm 7568d 13h /trunk/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7568d 13h /trunk/
115 Added signals for WB Master B3. tadejm 7568d 13h /trunk/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7575d 16h /trunk/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7575d 21h /trunk/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7577d 20h /trunk/
109 There was missing path to hdl.var file. tadejm 7581d 17h /trunk/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7581d 17h /trunk/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7581d 17h /trunk/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7586d 16h /trunk/
105 Wrong pci_bridge32.v file included in the project! mihad 7591d 23h /trunk/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7592d 01h /trunk/
103 Added test application and modified files to support it. mihad 7638d 23h /trunk/
102 Cleanup! mihad 7638d 23h /trunk/
101 Added simulation files. mihad 7638d 23h /trunk/
100 Cleanup! mihad 7638d 23h /trunk/
99 Cleanup! mihad 7638d 23h /trunk/
98 Cleanup. mihad 7638d 23h /trunk/
97 Doing a little bit of cleanup. mihad 7638d 23h /trunk/
96 Update! mihad 7639d 00h /trunk/
95 Removed this file, because it was too large - long download time. mihad 7639d 00h /trunk/
94 Changed one critical PCI bus signal logic. mihad 7639d 00h /trunk/
93 Added a test application! mihad 7639d 07h /trunk/
92 Update! mihad 7639d 07h /trunk/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7674d 21h /trunk/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7674d 21h /trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.