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[/] [pci/] [tags/] [wb2hpi/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5543d 16h /pci/tags/wb2hpi/
141 This commit was manufactured by cvs2svn to create tag 'wb2hpi'. 7415d 12h /tags/wb2hpi/
140 Update! SPOCI Implemented! mihad 7415d 12h /trunk/
139 Added for SPOCI testing! mihad 7415d 12h /trunk/
138 added test_initial_all_conf_values
mbist_ctrl_i replaced by mbist_en_i
fr2201 7432d 06h /trunk/
137 def_wb_imagex_addr_map defined correctly fr2201 7442d 14h /trunk/
136 Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) fr2201 7442d 15h /trunk/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
mihad 7451d 13h /trunk/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.
mihad 7455d 12h /trunk/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7460d 12h /trunk/
128 Some warning cleanup. simons 7461d 14h /trunk/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7469d 08h /trunk/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7507d 14h /trunk/
122 mbist signals updated according to newest convention markom 7514d 15h /trunk/
119 Added support for WB B3. Some testcases were updated. tadejm 7571d 03h /trunk/
118 Some minor changes due to changes in core. tadejm 7571d 03h /trunk/
117 WB Master is now WISHBONE B3 compatible. tadejm 7571d 03h /trunk/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7571d 03h /trunk/
115 Added signals for WB Master B3. tadejm 7571d 03h /trunk/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7578d 06h /trunk/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7578d 11h /trunk/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7580d 10h /trunk/
109 There was missing path to hdl.var file. tadejm 7584d 07h /trunk/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7584d 07h /trunk/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7584d 07h /trunk/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7589d 06h /trunk/
105 Wrong pci_bridge32.v file included in the project! mihad 7594d 13h /trunk/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7594d 16h /trunk/
103 Added test application and modified files to support it. mihad 7641d 13h /trunk/
102 Cleanup! mihad 7641d 13h /trunk/

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