URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [apps/] [crt/] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5548d 10h	/pci/trunk/apps/crt/
96	Update!	mihad	7646d 08h	/pci/trunk/apps/crt/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7682d 06h	/pci/trunk/apps/crt/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7682d 06h	/pci/trunk/apps/crt/
84	Changed vendor ID.	mihad	7740d 01h	/pci/trunk/apps/crt/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7782d 02h	/pci/trunk/apps/crt/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7785d 01h	/pci/trunk/apps/crt/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7788d 02h	/pci/trunk/apps/crt/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7901d 02h	/pci/trunk/apps/crt/
31	User defined constants used for Test Application	tadej	8120d 22h	/pci/trunk/apps/crt/
29	Xilinx synthesys log file	tadej	8121d 09h	/pci/trunk/apps/crt/
25	* empty log message *	mihad	8142d 00h	/pci/trunk/apps/crt/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8142d 03h	/pci/trunk/apps/crt/
14	* empty log message *	mihad	8142d 05h	/pci/trunk/apps/crt/
2	New project directory structure	mihad	8264d 03h	/pci/trunk/apps/crt/