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[/] [pci/] [trunk/] [sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5532d 13h /pci/trunk/sim/
152 Some regression tests were failing during completion expired testing. mihad 6968d 06h /trunk/sim/
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.
mihad 7196d 06h /trunk/sim/
140 Update! SPOCI Implemented! mihad 7404d 09h /trunk/sim/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
mihad 7440d 10h /trunk/sim/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.
mihad 7444d 09h /trunk/sim/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7496d 11h /trunk/sim/
118 Some minor changes due to changes in core. tadejm 7560d 00h /trunk/sim/
109 There was missing path to hdl.var file. tadejm 7573d 04h /trunk/sim/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7578d 03h /trunk/sim/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7583d 13h /trunk/sim/
95 Removed this file, because it was too large - long download time. mihad 7630d 11h /trunk/sim/
92 Update! mihad 7630d 19h /trunk/sim/
81 Updated synchronization in top level fifo modules. mihad 7762d 23h /trunk/sim/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7766d 04h /trunk/sim/
73 Bug fixes, testcases added. mihad 7772d 05h /trunk/sim/
72 *** empty log message *** mihad 7819d 09h /trunk/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7874d 11h /trunk/sim/
62 Added BIST signals for RAMs. mihad 7877d 04h /trunk/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7885d 04h /trunk/sim/

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