URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 74

Rev	Log message	Author	Age	Path
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7782d 01h	/
73	Bug fixes, testcases added.	mihad	7782d 01h	/
72	* empty log message *	mihad	7829d 05h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7836d 21h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7874d 04h	/
69	Changed BIST signal names etc..	mihad	7874d 04h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7877d 14h	/
67	Changed BIST signals for RAMs.	tadejm	7877d 19h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7881d 05h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7884d 03h	/
64	The testcase I just added in previous revision repaired	mihad	7884d 05h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7884d 07h	/
62	Added BIST signals for RAMs.	mihad	7887d 00h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7895d 00h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7895d 00h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7895d 01h	/
58	Removed all logic from asynchronous reset network	mihad	7900d 02h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7900d 07h	/
56	Number of state bits define was removed	mihad	7900d 22h	/
55	Changed state machine encoding to true one-hot	mihad	7900d 23h	/