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80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7773d 10h /
79 Updated. mihad 7773d 10h /
78 Old files with wrong names removed. mihad 7773d 10h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7773d 10h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7776d 09h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7779d 10h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7779d 10h /
73 Bug fixes, testcases added. mihad 7779d 10h /
72 *** empty log message *** mihad 7826d 14h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7834d 06h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7871d 14h /
69 Changed BIST signal names etc.. mihad 7871d 14h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7874d 23h /
67 Changed BIST signals for RAMs. tadejm 7875d 04h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7878d 14h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7881d 12h /
64 The testcase I just added in previous revision repaired mihad 7881d 15h /
63 Added additional testcase and changed rst name in BIST to trst mihad 7881d 16h /
62 Added BIST signals for RAMs. mihad 7884d 09h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7892d 09h /

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