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Subversion Repositories pit

[/] [pit/] - Rev 24

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Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4572d 18h	/pit/
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4658d 05h	/pit/
22	Correct revision, compiles with VCS.	rehayes	4658d 05h	/pit/
21	Simple language upgrade	rehayes	4658d 22h	/pit/
20	minor update for timing constraint sugestions.	rehayes	5193d 23h	/pit/
19	Minor change to add parameter to pit instance	rehayes	5194d 00h	/pit/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5194d 03h	/pit/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5207d 23h	/pit/
16	Added master error counter variable, added simulation timout limit	rehayes	5319d 02h	/pit/
15	Fix blocking assigment	rehayes	5347d 03h	/pit/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5416d 00h	/pit/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5446d 04h	/pit/
12	Fixed for single cycle reads	rehayes	5446d 23h	/pit/
11	Changed read task to capture data at rising edge of clock	rehayes	5446d 23h	/pit/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5448d 02h	/pit/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5453d 19h	/pit/
8	Fix ack signal in testbench	rehayes	5453d 20h	/pit/
7	Reflection of minor corrections	rehayes	5458d 02h	/pit/
6	Reflection of minor corrections	rehayes	5458d 02h	/pit/
5		rehayes	5495d 22h	/pit/

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Subversion Repositories pit

[/] [pit/] - Rev 24

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