URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] - Rev 24

Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4586d 18h	/
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4672d 05h	/
22	Correct revision, compiles with VCS.	rehayes	4672d 05h	/
21	Simple language upgrade	rehayes	4672d 21h	/
20	minor update for timing constraint sugestions.	rehayes	5207d 23h	/
19	Minor change to add parameter to pit instance	rehayes	5208d 00h	/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5208d 02h	/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5221d 23h	/
16	Added master error counter variable, added simulation timout limit	rehayes	5333d 01h	/
15	Fix blocking assigment	rehayes	5361d 02h	/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5430d 00h	/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5460d 04h	/
12	Fixed for single cycle reads	rehayes	5460d 23h	/
11	Changed read task to capture data at rising edge of clock	rehayes	5460d 23h	/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5462d 02h	/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5467d 19h	/
8	Fix ack signal in testbench	rehayes	5467d 20h	/
7	Reflection of minor corrections	rehayes	5472d 01h	/
6	Reflection of minor corrections	rehayes	5472d 02h	/
5		rehayes	5509d 21h	/