URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] - Rev 421

Rev	Log message	Author	Age	Path
404	Changed spacing	rhoads	4719d 07h	/plasma/trunk/vhdl/
403	Disable Ethernet and cache when simulating.	rhoads	4719d 07h	/plasma/trunk/vhdl/
397	Added RAM32X1D option	rhoads	4853d 01h	/plasma/trunk/vhdl/
391	Better fix for 0x8000000 * negative number	rhoads	5005d 07h	/plasma/trunk/vhdl/
390	Handle special case of signed mult of 0x80000000 and a negative number	rhoads	5008d 06h	/plasma/trunk/vhdl/
383	Permit up to 64KB internal RAM and updated cache code.	rhoads	5015d 07h	/plasma/trunk/vhdl/
377	Fix cache_we warning	rhoads	5158d 13h	/plasma/trunk/vhdl/
376	Add write_enable to sensitivity list for Altera	rhoads	5158d 14h	/plasma/trunk/vhdl/
374	Fixed comment	rhoads	5204d 03h	/plasma/trunk/vhdl/
371		rhoads	5353d 16h	/plasma/trunk/vhdl/
370	Fix "SLTIU v0, a0, -4000" by making imm signed	rhoads	5353d 17h	/plasma/trunk/vhdl/
369	Simplify E_RX_CLK usage	rhoads	5359d 04h	/plasma/trunk/vhdl/
365	Added UNISIM comment	rhoads	5417d 05h	/plasma/trunk/vhdl/
356	Added space to align text	rhoads	5469d 04h	/plasma/trunk/vhdl/
352		linus	5517d 21h	/plasma/trunk/vhdl/
350		root	5546d 16h	/plasma/trunk/vhdl/
348	Added comment for 32MB and 128MB DDR parts	rhoads	5577d 12h	/plasma/trunk/vhdl/
347	Xilinx ISE Project file	rhoads	5577d 12h	/plasma/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5614d 12h	/plasma/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5618d 08h	/plasma/trunk/vhdl/