OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [branches/] - Rev 59

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Remove branch: "new-privileged-isa" skordal 3234d 19h /potato/branches/
57 Add processor datasheet skordal 3234d 22h /potato/branches/
56 Remove old and outdated processor manual skordal 3234d 22h /potato/branches/
55 Use timer_clk for the example design and SoC testbench skordal 3235d 00h /potato/branches/
54 Update benchmarks to work with supervisor spec v1.7 skordal 3239d 14h /potato/branches/
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3241d 15h /potato/branches/
52 Correct .data section of sw-jal test skordal 3241d 15h /potato/branches/
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3241d 15h /potato/branches/
50 Update test environment to the new supervisor ISA skordal 3253d 15h /potato/branches/
49 Correct spelling of "privileged" skordal 3263d 15h /potato/branches/
48 Create branch for upgrading to the new privileged ISA skordal 3263d 15h /potato/branches/
46 Remove branch: cache-playground skordal 3266d 16h /potato/branches/
44 Add instruction cache and use the WB adapter as dmem interface skordal 3266d 17h /potato/branches/
43 Improve instruction fetch logic skordal 3266d 17h /potato/branches/
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3266d 17h /potato/branches/
41 Make continouous status register reads asynchronous skordal 3266d 17h /potato/branches/
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.
skordal 3266d 17h /potato/branches/
39 Disable IRQs when handling exceptions skordal 3266d 17h /potato/branches/
38 Add "Hello World" test application skordal 3266d 18h /potato/branches/
37 Add macro to set the TOHOST register from C code skordal 3266d 18h /potato/branches/
33 Ensure correct read of CSR after stall skordal 3266d 18h /potato/branches/
32 Prevent jumping/branching when stalling skordal 3269d 16h /potato/branches/
31 Prevent flushing the pipeline if it is stalling skordal 3269d 17h /potato/branches/
30 Add testcase for a combination of instructions that fail when using cache skordal 3271d 21h /potato/branches/
29 Add reset functionality for the WB arbiter state machine skordal 3274d 16h /potato/branches/
27 Prevent exceptions from being taken while stalling skordal 3280d 18h /potato/branches/
25 Add placeholder cache modules and a wishbone arbiter skordal 3283d 01h /potato/branches/
23 Create branch to use for implementing a cache skordal 3283d 14h /potato/branches/
1 The project and the structure was created root 3322d 06h /potato/branches/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.