OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] - Rev 66

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
66 Change UART status register to include recv buffer empty

This replaces bit 0 in the status register, previously used
for recv buffer _not_ empty, with a bit indicating if the
recv buffer _is_ empty.		 skordal 3100d 23h /potato/trunk/
65 Update platform headers and add cache control commands

Cache control is currently no-ops on Potato.		 skordal 3167d 07h /potato/trunk/
64 Add display enable support for the 7-seg module skordal 3167d 07h /potato/trunk/
63 Upgrade makefiles for use with the upgraded toolchain skordal 3170d 07h /potato/trunk/
62 Add a couple of missing signals to a sensitivity list skordal 3198d 08h /potato/trunk/
61 Add 7-segment display controller to the Potato SoC skordal 3199d 11h /potato/trunk/
60 Remove out-of-date comment skordal 3213d 03h /potato/trunk/
58 Merge branch new-privileged-isa (r48-r57) into trunk

This adds support for the newly published supervisor extensions
version 1.7. In addition, a processor datasheet has been added
and the timer_clk signal has been properly connected in the
example design and the SoC testbench.		 skordal 3233d 07h /potato/trunk/
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.		 skordal 3265d 02h /potato/trunk/
36 Ensure correct read of CSR after stall skordal 3265d 04h /potato/trunk/
35 Prevent jumping/branching when stalling skordal 3265d 04h /potato/trunk/
34 Prevent flushing the pipeline if it is stalling skordal 3265d 04h /potato/trunk/
28 Add rudimentary User's manual skordal 3279d 01h /potato/trunk/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.		 skordal 3279d 06h /potato/trunk/
24 Remove unused STRINGIFY macros skordal 3282d 00h /potato/trunk/
22 Fix the potato_get_badvaddr() macro skordal 3282d 00h /potato/trunk/
21 Upgrade the example design to use a 60 MHz system clock skordal 3282d 01h /potato/trunk/
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.		 skordal 3282d 01h /potato/trunk/
19 SHA256 benchmark: allow compiler to inline at will skordal 3282d 01h /potato/trunk/
18 instr_misalign_check: add do_jump to sensitivity list skordal 3284d 01h /potato/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.