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[/] [qspiflash/] [trunk/] [bench/] [cpp/] [eqspiflashsim.h] - Rev 16

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16 Added a full blown test bench to the controller

This includes:
- A global make file, and a "make test" which will build the test bench.
- Merging other versions of the QSPI flash driver I had lying around
- Grabbing the best of these, and verifying that they work
- The result is a reduction in overall logic
dgisselq 2753d 18h /qspiflash/trunk/bench/cpp/eqspiflashsim.h
14 Updates: little-big endian, various other fixes

1. Made the wbqspiflash.v and llqspi.v files compile with default_nettype none
2. Changed the internal flash representation to big endian. A little-big
endian conversion is now required when writing to the flash from a PC.
3. Simplified the address description via w_wb_addr and w_spif_addr, so that
the core is more flexible when changing sizes.
4. Removed the dependence upon the WB_CYC line ... as part of the WB
simplifications I've been doing.
5. Got XIP working for the EQSPI flash (I guess --- it's been a while since
I made those changes)
6. Adjusted (fixed) sim of read/writes to the volatile config register
(necessary for XIP)
dgisselq 2775d 01h /qspiflash/trunk/bench/cpp/eqspiflashsim.h
12 Adding the sources for the extended Quad SPI flash test bench. dgisselq 3044d 16h /qspiflash/trunk/bench/cpp/eqspiflashsim.h

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