OpenCores
URL https://opencores.org/ocsvn/qspiflash/qspiflash/trunk

Subversion Repositories qspiflash

[/] [qspiflash/] [trunk/] [rtl/] - Rev 23

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
23 Updated headers dgisselq 2073d 14h /qspiflash/trunk/rtl/
22 Read only is now an option of wbqspiflash

It was a macro before.
dgisselq 2073d 14h /qspiflash/trunk/rtl/
20 Changed reference to flash_config to flashconfig.v dgisselq 2547d 03h /qspiflash/trunk/rtl/
19 LLQSPI now passes formal tests dgisselq 2547d 03h /qspiflash/trunk/rtl/
18 Renamed the flash config file dgisselq 2547d 03h /qspiflash/trunk/rtl/
16 Added a full blown test bench to the controller

This includes:
- A global make file, and a "make test" which will build the test bench.
- Merging other versions of the QSPI flash driver I had lying around
- Grabbing the best of these, and verifying that they work
- The result is a reduction in overall logic
dgisselq 2689d 08h /qspiflash/trunk/rtl/
14 Updates: little-big endian, various other fixes

1. Made the wbqspiflash.v and llqspi.v files compile with default_nettype none
2. Changed the internal flash representation to big endian. A little-big
endian conversion is now required when writing to the flash from a PC.
3. Simplified the address description via w_wb_addr and w_spif_addr, so that
the core is more flexible when changing sizes.
4. Removed the dependence upon the WB_CYC line ... as part of the WB
simplifications I've been doing.
5. Got XIP working for the EQSPI flash (I guess --- it's been a while since
I made those changes)
6. Adjusted (fixed) sim of read/writes to the volatile config register
(necessary for XIP)
dgisselq 2710d 15h /qspiflash/trunk/rtl/
11 This code has been proven, and is currently working within an Arty platform. dgisselq 2980d 06h /qspiflash/trunk/rtl/
10 Switched to Quad Output mode by default. dgisselq 2997d 03h /qspiflash/trunk/rtl/
9 Minor changes to the baseline, FIRST RELEASE OF THE EQSPIFLASH controller!! dgisselq 2997d 05h /qspiflash/trunk/rtl/
8 Minor documentation edits. dgisselq 3228d 02h /qspiflash/trunk/rtl/
7 Added the ability to make the Quad/SPI flash run in read-only mode, in an
effort to reduce it's resource/LUT usage enough to run on a Digilent Cmod-S6.
dgisselq 3248d 12h /qspiflash/trunk/rtl/
4 FIXED: in the previous version, the first read of the device would always fail.
This was due to the fact that the Xilinx loader that read from the device
to load the Xilinx configuration left the Quad SPI flash chip in a high
data rate state. Thus, on reset, the first thing this core does it to
take the device out of the high data rate state.

Also, on a bus action waiting on a write to complete, the timing was
off. This has now been corrected. Reads (in both modes) should now
stall the bus (properly) while a write/erase cycle is ongoing, and
complete when finished.

The bug in high speed writing was traced to a read bug, not a write bug.
High speed (i.e. 4-bit transaction) writing has been re-enabled.

The bug in transitioning from 1-bit mode to 4-bit reads has been fixed.
This was causing the high speed write bug mentioned above.

Read ID was stalling the bus. This was traced to a sign error while
referencing the chip select line, and has been fixed.

The lowerlevel QSPI project was modified to add a holding state. We were
struggling with a bug whereby a late read would hang the device. The upper
level driver would issue it when the lower level driver was busy, and yet
think that it was accomplished. The lower level driver was moving from ready
to idle, so it never saw the read. Now, hold keeps the lower level driver
in the ready state at the end of a read until the bus transaction is complete,
or until it goes on to some other transaction other than reading data.
(This was a big change.)

Finally, unnecessary debugging lines were disabled in the simulator.
dgisselq 3428d 09h /qspiflash/trunk/rtl/
3 This quick update fixes some oopses associated with the original release.
Specifically, I made sure the license comments were available in all source
files, made sure all source files mentioned that they were a part of a Quad
SPI flash controller, rather than the Basys-3 development board project they
were originally a part of or the Spartan 3E project before that, I took out
the (undocumented) debug "scaffolding" that was still in the Verilog files,
and I added the C++ source for the bench test/simulator into the project.
Although the full bench test is not complete, it should be sufficient for
anyone who would wish to test this within Verilator.

These changes should not affect any of the functionality of the core.
dgisselq 3435d 02h /qspiflash/trunk/rtl/
2 Initial submission. dgisselq 3435d 03h /qspiflash/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.