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[/] [qspiflash/] [trunk/] [rtl/] [eqspiflash.v] - Rev 23

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16 Added a full blown test bench to the controller

This includes:
- A global make file, and a "make test" which will build the test bench.
- Merging other versions of the QSPI flash driver I had lying around
- Grabbing the best of these, and verifying that they work
- The result is a reduction in overall logic
dgisselq 841d 18h /qspiflash/trunk/rtl/eqspiflash.v
14 Updates: little-big endian, various other fixes

1. Made the wbqspiflash.v and llqspi.v files compile with default_nettype none
2. Changed the internal flash representation to big endian. A little-big
endian conversion is now required when writing to the flash from a PC.
3. Simplified the address description via w_wb_addr and w_spif_addr, so that
the core is more flexible when changing sizes.
4. Removed the dependence upon the WB_CYC line ... as part of the WB
simplifications I've been doing.
5. Got XIP working for the EQSPI flash (I guess --- it's been a while since
I made those changes)
6. Adjusted (fixed) sim of read/writes to the volatile config register
(necessary for XIP)
dgisselq 863d 01h /qspiflash/trunk/rtl/eqspiflash.v
11 This code has been proven, and is currently working within an Arty platform. dgisselq 1132d 16h /qspiflash/trunk/rtl/eqspiflash.v
10 Switched to Quad Output mode by default. dgisselq 1149d 13h /qspiflash/trunk/rtl/eqspiflash.v
9 Minor changes to the baseline, FIRST RELEASE OF THE EQSPIFLASH controller!! dgisselq 1149d 15h /qspiflash/trunk/rtl/eqspiflash.v

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