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URL https://opencores.org/ocsvn/r2000/r2000/trunk

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[/] [r2000/] [trunk/] - Rev 32

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Rev Log message Author Age Path
32 b ameziti 5399d 18h /r2000/trunk/
29 ameziti 5414d 19h /r2000/trunk/
28 ameziti 5415d 05h /r2000/trunk/
27 The design doesn't work correctly. ameziti 5415d 05h /r2000/trunk/
24 New directory structure. root 5551d 19h /r2000/trunk/
23 - when freeze or stall; don't let memory operations
- Modification on the CP0
- The CP0 is deplaced in the WB stage
- The INT, SI event signals are treated asynchronously in the WB stage
- The rCAUSE register is asynchronous now
- The wException signal is asyncronous instantanously
- Add a repeat/continous treatement (not completed yet)

- *** The "INT EXCEPTION NO STALL" work correctly		 ameziti 5910d 05h /trunk/
22 - Some modifications for testing exception. ameziti 5944d 21h /trunk/
21 - Flush must be on all signals in the pipeline. ameziti 5944d 21h /trunk/
20 - Modification of CP0 to wait the end of all stalls before to process Exception.
- Set "Exception sign" active until all Stalls are completed.		 ameziti 5945d 04h /trunk/
19 - Exception signals must be stalled, flushed, stoped or cleared(except reset)
- Look at 14-07-2007
- except the asynchronous event like "external interruption"		 ameziti 5945d 10h /trunk/
18 - Read/Write of the CP0 register is in the WB stage, but Exception detection begin from the MEM stage. ameziti 5945d 11h /trunk/
17 - UnFonctional Modifications: Change the name of the address port of "CP0". ameziti 5945d 11h /trunk/
16 - Remove All generable files from the project. ameziti 5945d 19h /trunk/
15 - UnFonctional Modifications.
- Change the "CP0" define to "EXCEPTION".		 ameziti 5945d 20h /trunk/
14 Remove unnecessary files from project. ameziti 5946d 04h /trunk/
13 - To simplify the exception traitement: Instruction are executed serialy.
- Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.		 ameziti 5946d 04h /trunk/
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 5946d 05h /trunk/
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 5946d 05h /trunk/
10 Modification of the CP0. ameziti 5946d 05h /trunk/
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5946d 05h /trunk/

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