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URL https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk

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[/] [rs232_interface/] [trunk/] - Rev 16

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16 Project's block diagram.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 4869d 20h /rs232_interface/trunk/
15 Removed uncompressed image with big size. akram.mashni 4869d 20h /rs232_interface/trunk/
14 Block diagram image of 2011-01-16 version.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 4869d 21h /rs232_interface/trunk/
13 Initial commit of documentation.
Created block diagram (OpenOffice Draw format).		 akram.mashni 4869d 21h /rs232_interface/trunk/
12 Updated news of uart.vhd commit. akram.mashni 4870d 23h /rs232_interface/trunk/
11 Moved debouncer to a new process.
Fixed rx_clk_en generation.
Fixed start of reception condition on rx FSM.		 akram.mashni 4871d 00h /rs232_interface/trunk/
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!		 akram.mashni 4878d 18h /rs232_interface/trunk/
9 Updated change log. akram.mashni 4916d 09h /rs232_interface/trunk/
8 Added Recommended Tools akram.mashni 4916d 09h /rs232_interface/trunk/
7 Implemented PARITY (not tested!). akram.mashni 4917d 19h /rs232_interface/trunk/
6 Fixed/improved header.
Changed SPACEs to TABs.		 akram.mashni 4919d 01h /rs232_interface/trunk/
5 Added comments to port map. akram.mashni 4926d 05h /rs232_interface/trunk/
4 Added "Change Log".
Added "About"		 akram.mashni 4926d 06h /rs232_interface/trunk/
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz		 akram.mashni 4926d 06h /rs232_interface/trunk/
2 Initial Commit luciorp 4982d 19h /rs232_interface/trunk/
1 The project and the structure was created root 5010d 16h /rs232_interface/trunk/

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