URL https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk

Subversion Repositories rtfsimpleuart

[/] [rtfsimpleuart/] [trunk/] [rtl/] [verilog/] [rtfSimpleUartTx.v] - Rev 15

Rev	Log message	Author	Age	Path
15	- Output 16x clk	robfinch	3062d 11h	/rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartTx.v
13	- updated license notice	robfinch	3823d 21h	/rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartTx.v
12	+BaudX8 mode !start frame detector - checks 1->0 transition !frame complectness - frame completes right after center of a frame bit, allows more difference of sender and reciever baud	AlexRayne	3824d 03h	/rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartTx.v
4	initial archive	robfinch	4620d 03h	/rtfsimpleuart/trunk/rtl/verilog/rtfSimpleUartTx.v