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Rev Log message Author Age Path
114 Change ownership albert.watson 2291d 10h /
113 S1_Core: Attempt to merge some long time changes Fab had on his backups. albert.watson 2598d 07h /
112 Slightly improved version of boot code as outlined by Emanuele Luzzu. albert.watson 4277d 00h /
111 albert.watson 4391d 04h /
110 Reduced the number of scripts, just one for sim and one for synth. albert.watson 4391d 04h /
109 Started working on scripts. albert.watson 4391d 06h /
108 Added 'trunk' to S1 root dir fafa1971 5508d 11h /
107 Added old uploaded documents to new repository. root 5578d 07h /
106 Added old uploaded documents to new repository. root 5578d 13h /
105 New directory structure. root 5578d 13h /
104 File no longer in use fafa1971 5675d 08h /
103 Changed almost everything to make our boot code work. fafa1971 5675d 10h /
102 This version correctly initializes the SPARC Core and then jumps at address 0x144000 on Bank 0. fafa1971 5676d 01h /
101 Should assign all the 4 bits of completion signal the same value. fafa1971 5680d 07h /
100 SPU removed by hand. fafa1971 5680d 07h /
99 This bridge follows the rules stated in paragraph 6.8 of book "OpenSPARC Internals"
in order to stall all the threads while serving a single request.
fafa1971 5681d 00h /
98 Added stall/resume signals from bridge to SPARC Core. fafa1971 5681d 00h /
97 Changed hack to insert stall signal into the core (following OpenSPARC Internals book) fafa1971 5681d 00h /
96 File lists with updated SPARC Core code. fafa1971 5696d 06h /
95 Files from OpenSPARCT1.1.6 with the SPU instance removed from the sparc.v top-level. fafa1971 5696d 06h /

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