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20 This linker description file acknowledges a .fixdata section which can be
used for debug data upon startup. This allows a startup function to write
all registers out, without destroying them or modifying them on the way.
dgisselq 2966d 20h /s6soc/
19 Addition of dumpuart.cpp to dump the UART transactions to a FILE (method of
debugging the board). FLASHDRVR and ZIPLOAD were also updated to handle
loading ELF files where the code is longer than a single block.
dgisselq 2966d 20h /s6soc/
18 Added a picture of the device pinouts to the specification. dgisselq 2966d 20h /s6soc/
17 Modifications necessary to find some bugs, and to load the flash with an ELF
file.
dgisselq 2966d 20h /s6soc/
16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.
dgisselq 2966d 21h /s6soc/
15 Adds a new program and a new device: doorbell2 and the PmodCLS display. This
also includes a real-time clock simulator--since we couldn't fit it on the
board.
dgisselq 2972d 14h /s6soc/
14 Modified the loader so that it will load even if there are RAM variables
in the load, just as long as they aren't anything but zero. (The startup code,
however, doesn't clear memory to match--so be sure to initialize all variables.)
dgisselq 2972d 14h /s6soc/
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.
dgisselq 2972d 14h /s6soc/
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.
dgisselq 2973d 12h /s6soc/
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.
dgisselq 2974d 10h /s6soc/
10 Added the capability to run ELF files natively, fully processing the ELF format. dgisselq 2974d 10h /s6soc/
9 Added pinout diagrams, based upon a (hopefully) final UCF file. dgisselq 2974d 10h /s6soc/
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.
dgisselq 2979d 10h /s6soc/
7 Created/added an initial specification. Updated/corrected several copywrite
notices.
dgisselq 2980d 01h /s6soc/
6 Initial UCF modifications. Pin layout still isn't complete, but I'm starting
to work it.
dgisselq 3000d 20h /s6soc/
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.
dgisselq 3000d 20h /s6soc/
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.
dgisselq 3000d 20h /s6soc/
3 Updated date. dgisselq 3000d 20h /s6soc/
2 The initial check in--all the files that will make this SoC work. dgisselq 3011d 15h /s6soc/
1 The project and the structure was created root 3011d 16h /s6soc/

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